1. Field of the Invention
The present invention relates to a method of fabricating a flash memory device, and more specifically, to a method of fabricating a flash memory device, wherein a thickness and width of bit lines can be formed uniformly.
2. Discussion of Related Art
In a flash memory device, bit lines are formed in such a manner that an oxide film is deposited on a semiconductor substrate in which predetermined underlying patterns such as a gate, a source contact and a drain contact are formed, trenches are formed in the oxide film, the trenches are filled with a metal film, and chemical mechanical polishing (CMP) is performed on the metal film.
A thickness and width of the bit lines decide bit line resistance and capacitance values. It is thus possible to constantly maintain the bit line resistance and capacitance values by controlling a thickness and width of the oxide film.
The irregularity of a bit line width is incurred due to loss of an oxide film on the sides of trenches in a cleaning process that is performed before a metal film formation process after the trenches are formed. In order to prevent this, a wet barrier is formed on the sides of the trenches using a nitride film. Since the nitride film has a dielectric constant higher than that of the oxide film, however, there is a problem in that bit line capacitance increases due to the wet barrier.
Meanwhile, the irregularity in a thickness of a bit line is caused by loss of an oxide film in a trench etch process or a metal film CMP process. In order to prevent this, a CMP stop layer and an etch stop layer must be formed at the top and bottom of the oxide film, respectively.
A CMP stop layer and an etch stop layer are lost due to a wet chemical used in a cleaning process, which is performed before a metal film formation process after trenches are formed. Therefore, the irregularity problem of bit line thickness still remains unsolved.
The irregularity problem in a thickness and width of bit lines becomes more profound as a device shrinks, and causes the irregularity of bit line resistance and capacitance, which leads to degraded device characteristics.